EE Times - - Samsung Electronics Co. said Wednesday that it has packed 16 NAND die into a multi-chip package that will max out at a density of 16 gigabytes, ideal for memory hungry consumer electronics devices.
Samsung was able to thin its wafers to 30 microns to achieve the goal, or about 65 percent of the thickness of wafers used in its current offering of 10 die in an MCP. (A human cell is about 20-30 microns.) Samsung engineers used lasers to slice up the delicate wafers, which were too thin for the traditional wafer saws used to cut wafers of around 80 microns thick.
Samsung also changed up the traditional method of wafer bonding. Instead of running wires from both sides of the chip, only one side is used for contacts, with the die stacked off-center, in a zigzag pattern, to save space and shorten the wire connections.
The adhesive bonding the chips was also thinned to 20 microns, bringing the height of a 16-die stack to 1.4mm. In contrast, Samsung's 10-chip MCP uses a 60-micron adhesive layer and has a height of 1.6mm.
Samsung did not offer details on when the MCP would hit the market.
In September, Samsung also pushed into the lead on density of NAND flash, trotting out a 32-Gbit chip made on 40-nanometer. That trumped an earlier release by IM Flash Technologies LLC, a joint venture of Intel Corp. and Micron Technology Inc., which had previously one-upped Samsung by sampling a 4-Gbit NAND flash memory in a 50-nm process.
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The operation was accomplished successfully against the Saudi
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